1. Field of the Invention
The present invention pertains to the process of producing a dual damascene structure used for the interconnect architecture of semiconductor chips. More specifically this invention addresses the novel use of imprint lithography for fabricating dual damascene structures in a dielectric and the novel fabrication of dual damascene structured molds for improved manufacturing throughput, process simplification, and cost reduction, and equipment to implement dual damascene imprint lithographic methods.
2. Description of Related Art
The conventional lithographic process involves the projection of a pattern from a mask onto a substrate wherein the mask comprises a set or series of patterns consisting of opaque and transparent regions. The substrate contains a photosensitive polymer thereon. There are two types of photoresists: positive and negative which are explained in greater detail below.
The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) requires metallic wiring that connects individual devices in a semiconductor chip, to one another. The resultant product of one method of creating this wiring network on a small scale is the dual damascene (DD) process schematically shown in FIG. 1. An alternative depiction of this type product is disclosed in Deal, M; et al.; Silicon VLSI Technology: Fundamentals, Practice, and Modeling, Prentice, Upper Saddle River N.J. (2000) p. 724.
In FIG. 1a, depicting a cross section of a product of the standard DD1 process, an interlayer dielectric (ILD), shown as two layers PA1-110, PA1-120 is coated on the substrate PA1-100, FIG. 1a. The via level dielectric PA1-110 and the line level dielectric PA1-120 are shown separately for clarity of the process flow description. In general, these two layers can be made of the same or different insulating films, and in the former case, can be applied as a single monolithic layer. A hard mask layer(s) PA1-130 is optionally employed to facilitate etch selectivity and to serve as a polish stop as will be discussed later.
The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip in a horizontal plane, and the via features which connect lines in different levels together in a vertical plane. Historically, both layers are made from an inorganic glass-like silicon dioxide (SiO2) or a fluorinated silica film deposited by plasma enhanced chemical vapor deposition (PECVD).
In the conventional dual damascene process, the position of the horizontal lines PA1-150 and the vertical vias PA1-170 are defined lithographically in photoresist layers, PA1-140, depicted in FIGS. 1b and 1d respectively, and transferred into the hard mask and ILD layers using reactive ion etching processes.
The results of the process sequence shown in FIG. 1c is called a “line-first” approach because the trench PA1-160 which will house the line feature is etched first. After the trench formation, lithography is used to define a via pattern PA1-170 in the photoresist layer PA1-140, which is transferred into the dielectric material to generate a via opening PA1-180, FIG. 1d. The dual damascene trench and via structure PA1-190 is shown in FIG. 1e after the photoresist has been stripped. This structure PA1-190 is coated with a conducting liner material or material stack PA1-200 that serves to protect the conductor metal lines and vias and serve as an adhesion layer between the conductor and the ILD. This recess is then filled with a conducting fill material PA1-210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper, although other methods such as CVD and other materials such as Al or Au can also be used. The fill and liner materials are then chemically-mechanically polished (CMP) to be coplanar with the surface of the hard mask and the structure at this stage is shown in FIG. 1f. 
A capping material PA1-220 is deposited over the metal or as a blanket film, as is depicted in FIG. 1g to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional ILD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material PA1-220. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are defined to form a conductor in-lay within an insulator by a single polish step, this process is designated a dual damascene process.
Printed publications which provide a background for the present invention and which are hereby incorporated by reference and made a part of this disclosure are: U.S. Pat. No. 6,696,224, Template for Room Temperature, Low Pressure Micro- and Nano-Print Lithography; U.S. Pat. No. 6,334,960, Step and Flash Imprint Lithography; U.S. Publication Application Number 20020098426; High-Resolution Overlay Alignment Methods and Systems for Imprint Lithography; U.S. Publication Application Number 20020094496 Method and System of Automatic Fluid Dispensing for Imprint Lithography; U.S. Publication Application Number 20020093122, Methods for High Precision Gap and Orientation Sensing Between a Transparent Template and Substrate for Imprint Lithography; U.S. Publication Application Number 20040022888, Alignment Systems for Imprint Lithography; U.S. Publication Application Number 20040021254, Alignment Methods for Imprint Lithography; U.S. Publication Application Number 20040009673, Method and System for Imprint Lithography Using an Electric Field; U.S. Publication Application Number 20040008334, Step and Repeat Imprint Lithography Systems; U.S. Publication Application Number 20040007799, Formation of Discontinuous Films During an Imprint Lithography Process; U.S. Publication Application Number 20020115002, Template for Room Temperature, Low Pressure Micro- and Nano-imprint Lithography, U.S. Publication Application Number 20020098426, High Resolution Overlay Alignment Methods and Systems for Imprint Lithography, U.S. Publication Application Number 20020094496, Method and System of Automatic Fluid Dispensing for Imprint Lithography Processes; U.S. Publication Application Number 20020093122, Methods for High-Precision Gap and Orientation Sensing Between a Transparent Template and Substrate for Imprint Lithography.